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Презентация на тему Chapter 1computer system overview
Содержание
- 2. RoadmapBasic ElementsProcessor RegistersInstruction ExecutionInterruptsThe Memory HierarchyCache MemoryI/O Communication Techniques
- 3. Operating SystemExploits the hardware resources of one
- 4. A Computer’s Basic ElementsProcessorMain MemoryI/O ModulesSystem Bus
- 5. ProcessorControls operation, performs data processingTwo internal registersMemory
- 6. Main MemoryVolatileData is typically lost when power
- 7. I/O ModulesMoves data between the computer and
- 8. System BusCommunication among processors, main memory, and I/O modules
- 9. Top-Level View
- 10. RoadmapBasic ElementsProcessor RegistersInstruction ExecutionInterruptsThe Memory HierarchyCache MemoryI/O Communication Techniques
- 11. Processor RegistersFaster and smaller than main memoryUser-visible
- 12. User-Visible RegistersMay be referenced by machine languageAvailable
- 13. Data and Address RegistersDataOften general purposeBut some restrictions may applyAddressIndex RegisterSegment pointerStack pointer
- 14. Control and Status RegistersProgram counter (PC)Contains
- 15. RoadmapBasic ElementsProcessor RegistersInstruction ExecutionInterruptsThe Memory HierarchyCache MemoryI/O Communication Techniques
- 16. Instruction ExecutionA program consists of a set
- 17. Basic Instruction Cycle
- 18. Instruction Fetch and ExecuteThe processor fetches
- 19. Instruction RegisterFetched instruction loaded into instruction registerCategoriesProcessor-memory, processor-I/O, Data processing, Control
- 20. Characteristics of a Hypothetical Machine
- 21. Example of Program Execution
- 22. RoadmapBasic ElementsProcessor RegistersInstruction ExecutionInterruptsThe Memory HierarchyCache MemoryI/O Communication Techniques
- 23. InterruptsInterrupt the normal sequencing of the processorProvided
- 24. Common Classes of Interrupts
- 25. Flow of Control without Interrupts
- 26. Interrupts and the Instruction Cycle
- 27. Transfer of Control via Interrupts
- 28. Instruction Cycle with Interrupts
- 29. Short I/O Wait
- 30. Long I/O wait
- 31. Simple Interrupt Processing
- 32. Changes in Memory and Registers for an Interrupt
- 33. Multiple InterruptsSuppose an interrupt occurs while another
- 34. Sequential Interrupt Processing
- 35. Nested Interrupt Processing
- 36. Example of Nested Interrupts
- 37. MultiprogrammingProcessor has more than one program to
- 38. RoadmapBasic ElementsProcessor RegistersInstruction ExecutionInterruptsThe Memory HierarchyCache MemoryI/O Communication Techniques
- 39. Memory HierarchyMajor constraints in memoryAmountSpeedExpenseFaster access time,
- 40. The Memory HierarchyGoing down the hierarchyDecreasing cost
- 41. Secondary MemoryAuxiliary memoryExternalNonvolatileUsed to store program and data files
- 42. RoadmapBasic ElementsProcessor RegistersInstruction ExecutionInterruptsThe Memory HierarchyCache MemoryI/O Communication Techniques
- 43. Cache MemoryInvisible to the OSInteracts with other
- 44. Principal of LocalityMore details later but in
- 45. Cache and Main Memory
- 46. Cache PrinciplesContains copy of a portion of
- 47. Cache/Main-Memory Structure
- 48. Cache Read Operation
- 49. Cache Design IssuesMain categories are:Cache sizeBlock sizeMapping functionReplacement algorithmWrite policy
- 50. Size issuesCache sizeSmall caches have significant impact
- 51. Mapping functionDetermines which cache location the block
- 52. Replacement AlgorithmChooses which block to replace when
- 53. Write policyDictates when the memory write operation
- 54. RoadmapBasic ElementsProcessor RegistersInstruction ExecutionInterruptsThe Memory HierarchyCache MemoryI/O Communication Techniques
- 55. I/O TechniquesWhen the processor encounters an instruction
- 56. Programmed I/OThe I/O module performs the requested
- 57. Programmed I/O Instruction SetControlUsed to activate and instruct deviceStatusTests status conditionsTransferRead/write between process register and device
- 58. Programmed I/O ExampleData read in a
- 59. Interrupt-Driven I/OProcessor issues an I/O command to
- 60. Interrupt- Driven I/OEliminates needless waitingBut everything passes through processor.
- 61. Direct Memory AccessPerformed by a separate module
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- 63. Похожие презентации
RoadmapBasic ElementsProcessor RegistersInstruction ExecutionInterruptsThe Memory HierarchyCache MemoryI/O Communication Techniques
Слайд 2
Roadmap
Basic Elements
Processor Registers
Instruction Execution
Interrupts
The Memory Hierarchy
Cache Memory
I/O Communication
Techniques
Слайд 3
Operating System
Exploits the hardware resources of one or
more processors
Provides a set of services to system users
Manages
secondary memory and I/O devices
Слайд 5
Processor
Controls operation, performs data processing
Two internal registers
Memory address
resister (MAR)
Memory buffer register (MBR)
I/O address register
I/O buffer register
Слайд 6
Main Memory
Volatile
Data is typically lost when power is
removed
Referred to as real memory or primary memory
Consists of
a set of locations defined by sequentially numbers addressesContaining either data or instructions
Слайд 7
I/O Modules
Moves data between the computer and the
external environment such as:
Storage (e.g. hard drive)
Communications equipment
Terminals
Specified by
an I/O Address Register (I/OAR)
Слайд 10
Roadmap
Basic Elements
Processor Registers
Instruction Execution
Interrupts
The Memory Hierarchy
Cache Memory
I/O Communication
Techniques
Слайд 11
Processor Registers
Faster and smaller than main memory
User-visible registers
Enable
programmer to minimize main memory references by optimizing register
useControl and status registers
Used by processor to control operating of the processor
Used by privileged OS routines to control the execution of programs
Слайд 12
User-Visible Registers
May be referenced by machine language
Available to
all programs – application programs and system programs
Types of
registers typically available are:data,
address,
condition code registers.
Слайд 13
Data and
Address Registers
Data
Often general purpose
But some restrictions
may apply
Address
Index Register
Segment pointer
Stack pointer
Слайд 14
Control and
Status Registers
Program counter (PC)
Contains the address
of an instruction to be fetched
Instruction register (IR)
Contains the
instruction most recently fetchedProgram status word (PSW)
Contains status information
Слайд 15
Roadmap
Basic Elements
Processor Registers
Instruction Execution
Interrupts
The Memory Hierarchy
Cache Memory
I/O Communication
Techniques
Слайд 16
Instruction Execution
A program consists of a set of
instructions stored in memory
Two steps
Processor reads (fetches) instructions from
memoryProcessor executes each instruction
Слайд 18
Instruction Fetch
and Execute
The processor fetches the instruction
from memory
Program counter (PC) holds address of the instruction
to be fetched nextPC is incremented after each fetch
Слайд 19
Instruction Register
Fetched instruction loaded into instruction register
Categories
Processor-memory,
processor-I/O,
Data processing,
Control
Слайд 22
Roadmap
Basic Elements
Processor Registers
Instruction Execution
Interrupts
The Memory Hierarchy
Cache Memory
I/O Communication
Techniques
Слайд 23
Interrupts
Interrupt the normal sequencing of the processor
Provided to
improve processor utilization
Most I/O devices are slower than the
processorProcessor must pause to wait for device
Слайд 33
Multiple Interrupts
Suppose an interrupt occurs while another interrupt
is being processed.
E.g. printing data being received via communications
line.Two approaches:
Disable interrupts during interrupt processing
Use a priority scheme.
Слайд 37
Multiprogramming
Processor has more than one program to execute
The
sequence the programs are executed depend on their relative
priority and whether they are waiting for I/OAfter an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt
Слайд 38
Roadmap
Basic Elements
Processor Registers
Instruction Execution
Interrupts
The Memory Hierarchy
Cache Memory
I/O Communication
Techniques
Слайд 39
Memory Hierarchy
Major constraints in memory
Amount
Speed
Expense
Faster access time, greater
cost per bit
Greater capacity, smaller cost per bit
Greater capacity,
slower access speed
Слайд 40
The Memory Hierarchy
Going down the hierarchy
Decreasing cost per
bit
Increasing capacity
Increasing access time
Decreasing frequency of access to the
memory by the processor
Слайд 42
Roadmap
Basic Elements
Processor Registers
Instruction Execution
Interrupts
The Memory Hierarchy
Cache Memory
I/O Communication
Techniques
Слайд 43
Cache Memory
Invisible to the OS
Interacts with other memory
management hardware
Processor must access memory at least once per
instruction cycleProcessor speed faster than memory access speed
Exploit the principle of locality with a small fast memory
Слайд 44
Principal of Locality
More details later but in short
…
Data which is required soon is often close to
the current dataIf data is referenced, then it’s neighbour might be needed soon.
Слайд 46
Cache Principles
Contains copy of a portion of main
memory
Processor first checks cache
If not found, block of memory
read into cacheBecause of locality of reference, likely future memory references are in that block
Слайд 49
Cache Design Issues
Main categories are:
Cache size
Block size
Mapping function
Replacement
algorithm
Write policy
Слайд 50
Size issues
Cache size
Small caches have significant impact on
performance
Block size
The unit of data exchanged between cache and
main memoryLarger block size means more hits
But too large reduces chance of reuse.
Слайд 51
Mapping function
Determines which cache location the block will
occupy
Two constraints:
When one block read in, another may need
to be replacedComplexity of mapping function increases circuitry costs for searching.
Слайд 52
Replacement Algorithm
Chooses which block to replace when a
new block is to be loaded into the cache.
Ideally
replacing a block that isn’t likely to be needed againImpossible to guarantee
Effective strategy is to replace a block that has been used less than others
Least Recently Used (LRU)
Слайд 53
Write policy
Dictates when the memory write operation takes
place
Can occur every time the block is updated
Can occur
when the block is replacedMinimize write operations
Leave main memory in an obsolete state
Слайд 54
Roadmap
Basic Elements
Processor Registers
Instruction Execution
Interrupts
The Memory Hierarchy
Cache Memory
I/O Communication
Techniques
Слайд 55
I/O Techniques
When the processor encounters an instruction relating
to I/O,
it executes that instruction by issuing a
command to the appropriate I/O module.Three techniques are possible for I/O operations:
Programmed I/O
Interrupt-driven I/O
Direct memory access (DMA)
Слайд 56
Programmed I/O
The I/O module performs the requested action
then sets the appropriate bits in the I/O status
register but takes no further action to alert the processor.
As there are no interrupts, the processor must determine when the instruction is complete
Слайд 57
Programmed I/O
Instruction Set
Control
Used to activate and instruct device
Status
Tests
status conditions
Transfer
Read/write between process register and device
Слайд 58
Programmed
I/O Example
Data read in a word at
a time
Processor remains in status-checking look while reading
Слайд 59
Interrupt-Driven I/O
Processor issues an I/O command to a
module
and then goes on to do some other
useful work.The I/O module will then interrupt the processor to request service when it is ready to exchange data with the processor.
Слайд 61
Direct Memory Access
Performed by a separate module on
the system
When needing to read/write processor issues a command
to DMA module with:Whether a read or write is requested
The address of the I/O device involved
The starting location in memory to read/write
The number of words to be read/written
