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Презентация на тему Programmable Logic and FPGA

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2. ObjectivesWhat is a programmable logicWhat is an FPGAStructureSpecial functionsComparison and UsagesAltera Cyclone II 20 FPGADesign Flow
3. Semiconductor Chips FPGA & CPLDASICsApplication Specific Integrated CircuitsMicroprocessors Microcontrollers
4. Programmable logicAn integrated circuit that can be
5. AdvantagesShort Development timeReconfigurableSaves board spaceFlexible to changesNo
6. How it Began : PLAProgrammable Logic ArrayFirst programmable device 2-level and-or structure One time programmable
7. SPLD - CPLDSimple Programmable logic deviceSingle AND LevelFlip-Flops and feedbacksComplex Programmable logic deviceSeveral PLDs Stacked together
8. FPGA - Field Programmable Gate ArrayProgrammable logic
9. Configuring LUTRequired FunctionTruth TableProgrammed LUTLUT is a
10. Special FPGA functionsInternal SRAMEmbedded Multipliers and
11. Comparison
12. UsagesDigital designs where ASIC is not commercialReconfigurable systemsUpgradeable systemsASIC prototyping and emulationEducation
13. ManufacturersXilinxAlteraLatticeActelWe will work with Altera FPGAs
14. Cyclone II - 2018,752 LEs 52 M4K
15. Cyclone II InternalsLogic ArrayM4K Memory BlocksEmbedded MultipliersPhase-Locked LoopsI/O Elements
16. Cyclone II Logic ArrayBuild of LABs (logic array blocks) and reconfigurable interconnect
17. Cyclone II Logic Array Block (LAB)16 LEsLocal
18. Cyclone II Logic Element (LE)
19. LE in Normal ModeSuitable for general logic applications and combinational functions.
20. LE in Arithmetic ModeIdeal for implementing adders, counters, accumulators, and comparators.
21. Cyclone II I/O FeaturesIn/Out/Tri-stateDifferent Voltages and I/O
22. Cyclone II I/O Buffer
23. Cyclone II Clocking16 Global Clocks4 PLLs
24. Cyclone II PLL3 OutputsClock DivisionClock MultiplicationPhase shift
25. MemoryTrue Dual port RAM/ROM with dual clockVariable
26. Cyclone II Memory Structure
27. Cyclone II Multipliers18x18 or 2 9x9 modes Up to 250MHz Performance
28. Delays and maximal frequencyGate delay – Delay
29. Design flow
30. Design Rules
31. Скачать презентацию
32. Похожие презентации

ObjectivesWhat is a programmable logicWhat is an FPGAStructureSpecial functionsComparison and UsagesAltera Cyclone II 20 FPGADesign Flow

Programmable logic and FPGACPU ArchitectureSerge Karabchevsky

Semiconductor Chips FPGA & CPLDASICsApplication Specific Integrated CircuitsMicroprocessors Microcontrollers

Programmable logicAn integrated circuit that can be programmed/reprogrammed with a digital logic

AdvantagesShort Development timeReconfigurableSaves board spaceFlexible to changesNo need for ASIC expensive design

How it Began : PLAProgrammable Logic ArrayFirst programmable device 2-level and-or structure One time programmable

SPLD - CPLDSimple Programmable logic deviceSingle AND LevelFlip-Flops and feedbacksComplex Programmable logic deviceSeveral PLDs Stacked together

FPGA - Field Programmable Gate ArrayProgrammable logic blocks (Logic Element “LE”) Implement

Configuring LUTRequired FunctionTruth TableProgrammed LUTLUT is a RAM with data width of

Special FPGA functionsInternal SRAMEmbedded Multipliers and DSP blocksEmbedded logic analyzerEmbedded CPUsHigh

UsagesDigital designs where ASIC is not commercialReconfigurable systemsUpgradeable systemsASIC prototyping and emulationEducation

ManufacturersXilinxAlteraLatticeActelWe will work with Altera FPGAs

Cyclone II - 2018,752 LEs 52 M4K RAM blocks 240K total RAM

Cyclone II InternalsLogic ArrayM4K Memory BlocksEmbedded MultipliersPhase-Locked LoopsI/O Elements

Cyclone II Logic ArrayBuild of LABs (logic array blocks) and reconfigurable interconnect

Cyclone II Logic Array Block (LAB)16 LEsLocal InterconnectLE carry chainsRegister chainsLAB Control

LE in Normal ModeSuitable for general logic applications and combinational functions.

LE in Arithmetic ModeIdeal for implementing adders, counters, accumulators, and comparators.

Cyclone II I/O FeaturesIn/Out/Tri-stateDifferent Voltages and I/O StandardsFlip-flop optionPull-up resistorsDDR interfaceSeries resistorsBus

Cyclone II Clocking16 Global Clocks4 PLLs

Cyclone II PLL3 OutputsClock DivisionClock MultiplicationPhase shift

MemoryTrue Dual port RAM/ROM with dual clockVariable data width 4K×1, 2K×2, 1K×4,

Cyclone II Multipliers18x18 or 2 9x9 modes Up to 250MHz Performance

Delays and maximal frequencyGate delay – Delay of logic element DFF delay

Слайды презентации

Слайд 2 Objectives
What is a programmable logic
What is an FPGA
Structure
Special

functions
Comparison and Usages
Altera Cyclone II 20 FPGA
Design Flow

Слайд 3 Semiconductor Chips
FPGA & CPLD
ASICs
Application Specific
Integrated Circuits
Microprocessors

Microcontrollers

Слайд 4 Programmable logic
An integrated circuit that can be programmed/reprogrammed

Programmable logicAn integrated circuit that can be programmed/reprogrammed with a digital

with a digital logic of a curtain level.
Started at

late 70s and constantly growing
Now available of up to approximately 700K Flip-Flops in a single chip.

Слайд 5 Advantages
Short Development time
Reconfigurable
Saves board space
Flexible to changes
No need

AdvantagesShort Development timeReconfigurableSaves board spaceFlexible to changesNo need for ASIC expensive

for ASIC expensive design and production
Fast time to market
Bugs

can be fixed easily
Of the shelf solutions are available

Слайд 6 How it Began : PLA
Programmable Logic Array
First programmable

device
2-level and-or structure
One time programmable

Слайд 7 SPLD - CPLD
Simple Programmable logic device
Single AND Level
Flip-Flops

and feedbacks
Complex Programmable logic device
Several PLDs Stacked together

Слайд 8 FPGA - Field Programmable Gate Array
Programmable logic blocks

FPGA - Field Programmable Gate ArrayProgrammable logic blocks (Logic Element “LE”)

(Logic Element “LE”) Implement combinatorial and sequential logic. Based on

LUT and DFF.
Programmable I/O blocks Configurable I/Os for external connections supports various voltages and tri-states.
Programmable interconnect Wires to connect inputs , outputs and logic blocks.
clocks
short distance local connections
long distance connections across chip

Слайд 9 Configuring LUT
Required Function
Truth Table
Programmed LUT
LUT is a RAM

Configuring LUTRequired FunctionTruth TableProgrammed LUTLUT is a RAM with data width

with data width of 1bit.
The contents are programmed at

power up

Слайд 10 Special FPGA functions
Internal SRAM
Embedded Multipliers and DSP blocks
Embedded

Special FPGA functionsInternal SRAMEmbedded Multipliers and DSP blocksEmbedded logic analyzerEmbedded CPUsHigh speed I/O (~10GHz)DDR/DDRII/DDRIII SDRAM interfacesPLLs

logic analyzer
Embedded CPUs
High speed I/O (~10GHz)
DDR/DDRII/DDRIII SDRAM interfaces
PLLs

Слайд 11 Comparison

Слайд 12 Usages
Digital designs where ASIC is not commercial
Reconfigurable systems
Upgradeable

systems
ASIC prototyping and emulation
Education

Слайд 13 Manufacturers
Xilinx
Altera
Lattice
Actel

We will work with Altera FPGAs

Слайд 14 Cyclone II - 20
18,752 LEs
52 M4K RAM

Cyclone II - 2018,752 LEs 52 M4K RAM blocks 240K total

blocks
240K total RAM bits
52 9x9 embedded multipliers

4 PLLs
16 Clock networks
315 user I/O pins
SRAM Based volatile configuration

Слайд 15 Cyclone II Internals

Logic Array
M4K Memory Blocks
Embedded Multipliers

Phase-Locked Loops
I/O Elements

Слайд 16 Cyclone II Logic Array

Build of LABs (logic array

blocks) and reconfigurable interconnect

Слайд 17 Cyclone II Logic Array Block (LAB)
16 LEs
Local Interconnect
LE

Cyclone II Logic Array Block (LAB)16 LEsLocal InterconnectLE carry chainsRegister chainsLAB

carry chains
Register chains
LAB Control Signals
2 CLK
2 CLK ENA
2 ACLR
1

SCLR
1 SLOAD

Слайд 18 Cyclone II Logic Element (LE)

Слайд 19 LE in Normal Mode
Suitable for general logic applications

and combinational functions.

Слайд 20 LE in Arithmetic Mode
Ideal for implementing adders, counters,

accumulators, and comparators.

Слайд 21 Cyclone II I/O Features
In/Out/Tri-state
Different Voltages and I/O Standards
Flip-flop

Cyclone II I/O FeaturesIn/Out/Tri-stateDifferent Voltages and I/O StandardsFlip-flop optionPull-up resistorsDDR interfaceSeries

option
Pull-up resistors
DDR interface
Series resistors
Bus keeper
Drive strength control
Slew rate control
Single

ended/differential

Слайд 22 Cyclone II I/O Buffer

Слайд 23 Cyclone II Clocking
16 Global Clocks
4 PLLs

Слайд 24 Cyclone II PLL
3 Outputs
Clock Division
Clock Multiplication
Phase shift

Слайд 25 Memory
True Dual port RAM/ROM with dual clock
Variable data

MemoryTrue Dual port RAM/ROM with dual clockVariable data width 4K×1, 2K×2,

width
4K×1, 2K×2, 1K×4, 512×8, 512×9, 256×16, 256×18
128×32, 128×36

(not available in true dual-port mode)
Input data and address are registered
1 Clock Write latency
Output data can be registered
Read latency of 1 or 2 clocks
Byte Enable